FIG. 1 shows a circuit for generating rectangular signals with adjustable phase shift known from the prior art. The circuit comprises two comparators 11, 12 and two D-type flip-flops 13, 14. Each comparator 11, 12 receives a triangular ramp signal, provided by a signal generating device 15, at one of its comparison inputs, and a reference voltage Vref1, Vref2 at the other input. The output of each comparator 11, 12 is connected to a flip-flop 13, 14 that is connected as a divide-by-two frequency divider, and is active on the rising edge.
The operation of the circuit will be explained with reference to FIG. 2. The first timing diagram shows the appearance of the ramp signal. It is assumed that at time t0 all of the signals are in the low state.
At time t1, the value of the ramp signal Vrampe becomes higher than the value of the first reference voltage Vref1, the output signal Pwm1 of the first comparator 11 passes from the low state to the high state. This rising edge will trigger the first D-flip-flop 13 and its output signal IP1 will pass to the high state.
The same phenomenon will be reproduced with the second comparator 12 and the second flip-flop 14 at time t2 once the value of the ramp signal Vrampe becomes higher than the value of the second reference voltage Vref2.
At time t3, the value of the ramp signal returns to zero, the output Pwm1, Pwm2 of the two comparators 13, 14 passes from the high state to the low state. As the flip-flops 13, 14 are active on the rising edge, the signals IP1, IP2 as output from the latter remain unchanged.
At time t4, the value of the ramp signal Vrampe once more becomes higher than the value of the first reference voltage Vref1. The output of the first comparator 11 passes from the low state to the high state. This rising edge will trigger the first D-flip-flop 13 and its output signal IP1 will pass from the high state to the low state.
Likewise, the output signal from the second flip-flop 14 IP2 passes from the high state to the low state at time t5.
A problem arises when interference occurs in the output signal from a comparator. This scenario is illustrated in FIG. 3 via an example in which an interference pulse 30 occurs in the output signal Pwm1_Pb of the first comparator.
In this figure, the first timing diagram shows the ramp signal. The second and third timing diagrams show, respectively, the appearance of the signal as output from the first comparator Pwm1_Pb and the appearance of the signal as output IP1_Pb from the first D-flip-flop. The last timing diagram serves as a comparison and shows the form of the signal as output from the flip-flop in the case in which the signal as output from the comparator is not suffering from interference.
It should be noted that the rising edge of the interference triggers the flip-flop at the output of the comparator and permanently disrupts the output signal.
A problem also arises upon starting the circuit, at the moment of its power-up, as it is not known whether the flip-flops are in the high state or low state.
It is possible to force the flip-flops into the low state upon starting by virtue of the reset input of said flip-flops. However, these reset systems are random and the rise times of the reset functions are not reliable. Owing to the uncertainty of the reset, the ramp signal may, for example, start before the flip-flops are initiated. Thus, when the flip-flops are ready to start, we will find ourselves between the two rising edges and hence only one of the two rising edges will be taken into account upon starting. The two flip-flops will then be offset by 180°.
Another problem may arise if the two reset commands are not carried out at exactly the same instant.